This project discusses the extremely important role of employing a software-based self-testing in the microprocessor test and validation sequence as well as its fundamental potency in other digitally oriented testing mechanisms.
In this project we aim at using the different software-based self-testing techniques to evaluate the open ended LEON III -- a SPARC V8 hardware implementation which includes several hardware and software based optimizations in the processor level. The whole code base for LEON III is written in VHDL and bares the GPL free software license which is a license for software that respects the user's freedom. This project deals with the testing of the LEON III implementation of this architecture within the depths of the hardware with the concept of hardware testing by exploiting the nature of the instruction set. This technique is an excellent choice for testing the hardware considering the open nature of the LEON III implementation. With this testing sequence, we will be able to test out and evaluate the different segments like the memory, cache and the intricate pipelining stages of the architecture. We will see that we can precisely determine the cause of the different faults and their origins in the hardware. In this project, we will also be able to generate/inject our own faults by varying the VHDL architecture and letting the code generator/software-based self-testing module diagnose the cause of the problem. Hence, as a crux, the whole project works on assembly code generation which includes the software-based self-test for LEON III implementation of the SPARC V8 by only using the instruction set of the architecture.